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Exciting developments are on the way in the server technology realm, particularly with AMD’s next-generation Zen 6 architecture. Recent leaks have unveiled potential specifications that could change the landscape of server performance. With a focus on high core counts and advanced cache designs, these upcoming products could significantly outpace current offerings. So, what can we expect from AMD’s Zen 6 architecture? Let’s dive deeper into the details.
Unveiling the Zen 6 architecture
AMD is gearing up to introduce its Zen 6 architecture, which is rumored to revolutionize server capabilities. The Venice platform, as it’s being referred to, is expected to house up to an astonishing 256 cores based on the Zen 6c design. This substantial core count is complemented by an impressive 1GB of total L3 cache, excluding any additional 3D cache chiplets that may enhance performance further. However, it’s important to approach these specifications with a degree of skepticism, as the formal launch of these products is still likely a year or more away.
The current lineup of AMD’s EPYC 9005 CPUs, codenamed Turin, utilizes the SP5 socket and features a design reminiscent of Arm’s big.LITTLE architecture. These CPUs can reach up to 192 cores thanks to the inclusion of the denser Zen 4c and 5c cores. Moreover, AMD has introduced a cost-effective SP6 socket that currently supports its EPYC 8004 (Siena) offerings, which feature up to 64 Zen 4c cores. The anticipated compatibility with the upcoming Zen 5-based EPYC 8005 (Sorano) family adds to the excitement.
New socket designs and core configurations
As AMD progresses with the Zen 6 architecture, it’s rumored to introduce new socket designs: the SP7 and SP8. The SP7 socket is expected to support the forthcoming EPYC 9006 (Venice) CPUs, which are speculated to consist of up to 256 Zen 6c cores spread across eight CCDs (Core Complex Dies). This configuration translates to 32-core Zen 6c CCDs, with each CCD purportedly featuring 128MB of L3 cache, contributing to the total L3 cache of 1GB for the 256-core version.
On the other hand, the SP8 socket is anticipated to support configurations of up to 128 Zen 6C cores, with 128MB per CCD. The projections for standard Zen 6 options on the SP8 indicate the possibility of 96 cores, achieved through eight 12-core chiplets, and a total of 384MB of L3 cache. This leap in core density is likely attributed to the adoption of TSMC’s cutting-edge 2nm (N2) process node, which will also likely bring improvements in input/output capabilities, including more memory channels and increased PCIe lane counts.
Why the focus on higher core counts?
The drive towards higher core counts and larger caches is clear, especially considering the upcoming competition from Intel’s Diamond Rapids and Clearwater Forest Xeon processors. These new processors are expected to be some of the most sophisticated designs Intel has ever produced, pushing AMD to innovate even further. Furthermore, AMD is expected to adopt advanced packaging solutions from TSMC for the Zen 6 architecture, potentially using silicon interposers or bridges to enhance the connectivity between its CCDs and IODs (I/O Dies).
Considering AMD’s typical two-year cadence for architectural refreshes, we can anticipate the first Zen 6-based products to hit the market by the second half of 2026. This evolution in server technology promises to not only boost performance but also cater to the growing demands of data centers worldwide.
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Hassam Nasir, a passionate hardware enthusiast and tech editor, continues to explore the intricacies of CPU technologies and hardware news. When he’s not writing, he’s likely immersed in building a custom water-loop gaming rig or benchmarking the latest CPUs and GPUs, all in the name of fun.
For readers interested in more tech innovations, keep an eye out for the upcoming Baltra processors from Apple, designed for AI servers, and the Noctua NH-D15 G2, which has recently added offset mounting bars tailored for Arrow Lake CPUs, optimizing cooling performance.