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Understanding Intel’s high-na euv strategy
During the recent Intel Foundry Direct 2025 conference, Intel articulated its approach towards employing High-NA EUV technology in semiconductor manufacturing. This strategy is crucial as the company navigates challenges related to cost-effectiveness and technological readiness. Although Intel has not fully committed to deploying High-NA EUV in its production processes, it has developed a robust backup plan using standard Low-NA EUV technology for its upcoming 14A node.
Intel’s proactive approach includes the recent installation of a second High-NA EUV tool in its Oregon manufacturing facility. The company emphasizes that the new technology is progressing well, even though the High-NA machines, priced at approximately $400 million each, have yet to be used in a live production environment. This cautious approach aims to mitigate any potential risks associated with adopting new, unproven technologies.
Design compatibility and yield parity
According to Dr. Naga Chandrasekaran, Intel’s EVP, CTOO, and GM of Intel Foundry Technology and Manufacturing, the company retains the option to utilize either Low-NA or High-NA solutions for its 14A technology. This flexibility ensures that there will be no negative impact on customers, regardless of the path Intel chooses. Furthermore, data from the 18A and 14A processes indicate that both Low-NA and High-NA solutions yield comparable results, allowing Intel to make informed decisions about its manufacturing flows.
Intel plans to employ High-NA EUV selectively across a limited number of layers in the 14A node. The remaining layers will utilize other machines with different resolutions, minimizing the impact of this decision on the overall manufacturing process. This strategic choice assures customers that they will not need to alter their designs based on Intel’s production decisions, which alleviates concerns regarding the adoption of newer, less proven technologies.
Minimizing risks while maximizing innovation
Intel’s assertion that both production flows can achieve similar yields suggests that there will be minimal repercussions on time-to-market, even if High-NA EUV development encounters challenges. While multipatterning techniques traditionally reduce yields, Intel’s claim of yield parity reflects significant advancements in the field, particularly in overlay technology. This innovative approach positions Intel to maintain a competitive edge in the semiconductor industry.
Although the discussions surrounding High-NA EUV have largely centered on cost concerns, there are significant technological hurdles that must be overcome before these machines can be widely adopted. Challenges include optimizing complementary technologies such as resists, photomasks, and computational lithography, all of which are critical for the successful implementation of High-NA EUV. Nevertheless, Intel has taken the lead by integrating ASML’s machine early in the development phase and has successfully produced 30,000 wafers using High-NA lithography.
Cost efficiency through innovation
In a recent presentation, Intel representatives highlighted the cost-saving potential of High-NA EUV technology. By leveraging a single pass of High-NA EUV, the company can generate patterns comparable to those achieved through traditional methods that require multiple exposures and extensive processing steps. This streamlined approach not only simplifies the manufacturing flow but also enhances overall cost efficiency.
Moreover, High-NA EUV allows for the possibility of reducing the number of metal layers in chip design, leading to further performance improvements. While Intel did not specify whether its comparisons were based on full-reticle-sized prints, it is important to note that High-NA can only print half of a reticle at a time, necessitating stitching to create a seamless unit. In contrast, Low-NA EUV machines can process an entire reticle-sized die in a single print, showcasing the unique capabilities and limitations of each technology.
Learning from past challenges
Intel’s cautious approach is influenced by the lessons learned from its previous struggles with the 10nm node, which ultimately led to a loss of market leadership to competitors like TSMC. The company acknowledges that the challenges faced during the 10nm development were partly due to overcommitting to multiple new manufacturing techniques at once. As a result, the decision to develop an alternative Low-NA production flow is a strategic move aimed at avoiding similar pitfalls in the future.
In addition to its High-NA strategy, Intel has also prioritized the development of alternative solutions. For instance, the company has successfully introduced a new backside power delivery system with its 18A node, which is an industry first. By maintaining flexibility and implementing a robust risk management strategy, Intel is positioning itself for success in the ever-evolving semiconductor landscape.
Competitive landscape and future outlook
While Intel is actively exploring High-NA EUV technology, its main competitor, TSMC, has opted against utilizing this technology for its A14 node, leaving open questions about when TSMC might adopt High-NA EUV in mass production. Initially, Intel intended to implement High-NA with its 18A process, but rapid advancements in the 14A node led to a revision of those plans.
As the semiconductor industry continues to evolve, Intel’s strategic focus on High-NA EUV and its backup Low-NA flow highlights the delicate balance between innovation and risk management. By prioritizing flexibility and yield parity, Intel aims to navigate the complexities of semiconductor manufacturing while delivering reliable solutions to its customers.