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At the recent European Technology Symposium in Amsterdam, TSMC made clear its position on next-generation lithography tools, particularly the high-NA EUV systems. The company, a leader in semiconductor manufacturing, stated that it does not require these advanced lithography systems for its latest process nodes, such as A16 and A14. This decision highlights TSMC’s confidence in its existing technologies and its commitment to pushing the boundaries of semiconductor performance without necessarily relying on the latest equipment.
TSMC’s rationale behind not adopting high-na EUV
TSMC’s Deputy Co-COO, Kevin Zhang, addressed the recurring question of when the company would implement high-NA EUV technology. He emphasized that TSMC will consider adopting such systems only when they can provide substantial, measurable benefits. According to Zhang, the enhancements achieved with the A14 process are significant enough without the need for high-NA EUV tools. This reflects the company’s ongoing efforts to extend the life of current EUV technologies while maximizing performance through innovative design strategies.
A14 process and its impressive capabilities
The A14 process is a significant advancement for TSMC, utilizing second-generation nanosheet gate-all-around transistors along with an innovative standard cell architecture. TSMC claims that A14 can deliver up to 15% higher performance while maintaining the same power and complexity. Alternatively, it can offer a 25% to 30% reduction in power consumption at the same frequency. This is a remarkable achievement, especially considering the 20% increase in transistor density compared to the previous N2 node, and a staggering 23% increase for pure logic applications.
The full node advantage without high-na EUV
This substantial leap in performance and efficiency illustrates what is known in the industry as the ‘full node advantage’. Interestingly, TSMC maintains that it can achieve these results without high-NA EUV lithography tools, which are often viewed as essential for producing advanced chips with high yields. The A16 process, which is essentially an evolution of N2P utilizing a Super Power Rail for enhanced power delivery, also does not require high-NA EUV systems. This contrasts sharply with Intel’s plans to incorporate high-NA EUV tools into its upcoming manufacturing technologies.
Innovation in chip production techniques
When questioned about the reliance on multi-patterning techniques for the A14, Zhang could not disclose specific details. However, he did share that TSMC’s technology team has found a way to produce chips on a 1.4nm node without resorting to high-NA EUV tools, which typically offer an 8nm resolution. This resolution is quite impressive compared to the 13.5nm resolution provided by standard low-NA EUV systems. Such innovations underscore TSMC’s commitment to pushing the limits of what is possible in semiconductor manufacturing.
Future outlook for TSMC and high-na EUV
Looking ahead, TSMC’s A14 is set to enter mass production in 2028, and it will be succeeded by an iteration featuring SPR backside power delivery in 2029. Remarkably, it appears that TSMC will not require high-NA EUV tools for this successor node either. This positions TSMC in stark contrast to competitors like Intel, which is gearing up to implement high-NA EUV technologies as part of their future manufacturing processes. TSMC’s current trajectory suggests that they may not embrace high-NA EUV for mass production until at least 2030, if not later.